Apparatus and method for alpha blending of digital images

ABSTRACT

In the present invention, an apparatus and method for performing alpha blending calculations in a fast and efficient manner is disclosed. When implemented as an integrated circuit, the apparatus of the present invention occupies reduced area. The apparatus comprises a plurality of multiplexers and an adder. Each of multiplexers is configured to receive a bit value, α 1 , of the digital value alpha, α. Each of the plurality of multiplexers is configured to receive the first and second digital image values. Each of the plurality of multiplexers is also configured to direct to outputs of the multiplexers either the first or second digital image value responsive to the bit value, α i . Each of the outputs of the plurality of multiplexers is shifted left according to the order of the bit values, α i , to produce a plurality of left-shifted outputs. The adder is produces the sum of the left-shifted outputs.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of image processing.More particularly, the present invention relates to blending two sourcesof image data to form a resulting image.

BACKGROUND OF THE INVENTION

[0002] A digital image is made up of many pixels that are represented ina computer system as digital values. The pixels are typically arrangedin columns and rows such that the collected pixels form images to beperceived by a user. Pixels can be displayed as color or gray-scaleimages (also called black and white images). In a gray-scale image, eachpixels is represented by a luminance (also called intensity) value. Forexample, where luminance is expressed using eight digital bits, eachpixel is represented by a single unsigned byte with a range of 0 to 255,where 0 specifies the darkest pixel, 255 specifies the brightest pixels,and intermediate values specify intermediate luminance. Moreover, imagescan be represented in color format wherein chrominances and luminancesare specified. Chrominance (or color) can be represented using acollection of colors that when mixed together generate a perceivedcolor. For example, the colors red (R), green (G), and blue (B) can beused to display many different colors. Depending on the chromaticcontent of the individual colors, a color gamut is available from whichcolors can be generated.

[0003] Digital image technology finds many applications includingtelevision, video and computer graphics. In these types of applications,it can be straightforward to display any given image; however, manypossibilities exist when it becomes necessary to display two or moreimages over the same display area. Whereas to display either of twoimages as if it were placed on top of the other can be a simple task, itcan, however, be the case that a mix or blending of the images isnecessary. In the field of art to which it pertains, this mixing orblending is often achieved through a technique called alpha blending.Through the use of alpha blending, two or more images can beindividually displayed, but can also be partially displayed with oneimage dominating the other.

[0004] In computer graphics applications, for example, in computergames, blending of images is very important, however, for complex orfast-paced graphics, alpha blending calculations can becomecomputationally intensive. In certain applications, a screen can containmillions of individual pixels where each pixel must be refreshed every{fraction (1/60)}^(th) of a second. Moreover, many or all such pixelsmay require alpha blending calculation. Thus, there is a need for amethod for fast alpha blending calculations in systems incorporatingcomplex digital graphics. There is a further need for an apparatus thatcan produce fast alpha blending calculations through reduced hardware orreduced complexity hardware, software, or firmware.

SUMMARY OF THE INVENTION

[0005] The present invention discloses an apparatus and method forperforming alpha blending calculations in a fast and efficient manner.Moreover, when implemented as an integrated circuit, an apparatusaccording to the present invention occupies reduced chip area. In anembodiment of the invention, an apparatus is disclosed for performingalpha blending calculations on a first digital image value, X, and asecond digital image value, Y, according to a digital value, alpha (α),that approximates the quantity, αX+(1−α)Y. The α value has a fractionalpart of n digits, a most significant bit of α₁, and a least significantbit of α_(n−1), wherein the order of α_(i) is related to i. Theapparatus comprises a plurality of multiplexers and an adder. Each ofthe plurality of multiplexers is configured to receive a correspondingbit value, α_(i), of the digital value α. Moreover, each of theplurality of multiplexers is configured to receive the first and seconddigital image values. Still further, each of the plurality ofmultiplexers is configured to direct to outputs of the plurality ofmultiplexers either the first or second digital image value responsiveto the bit value, α_(i), of the digital value α. Each of the outputs ofthe plurality of multiplexers is shifted left according to the order ofthe bit values, α_(i), of a to produce a plurality of left-shiftedoutputs. The adder is configured to receive the plurality ofleft-shifted outputs and is further configured to produce the sum of theleft-shifted outputs.

[0006] In another embodiment of the invention, an apparatus is disclosedfor performing alpha blending calculations on a first digital imagevalue and a second digital image value according to a digital alpha (α)value. The α value has a fractional part of n digits, a most significantbit of α₁, and a least significant bit of α_(n−1), wherein the order ofα_(i) is related to i. The apparatus comprises a plurality ofmultiplexers and an adder. Each of the plurality of multiplexers isconfigured to receive a bit value, α_(i), of the digital value α.Moreover, each of the plurality of multiplexers is configured to receivefirst and second left-shifted digital image values. The first and secondleft-shifted digital image values are shifted left according to theorder of the bit values, α_(i), of α. Still further, each of theplurality of multiplexers is configured to produce a plurality ofleft-shifted outputs by directing to outputs of the plurality ofmultiplexers either the first or second left-shifted digital image valueresponsive to the bit value, α_(i), of α. The adder is configured toreceive the plurality of left-shifted outputs and is further configuredto produce the sum of the left-shifted outputs.

[0007] In another embodiment of the invention, the adder is a carry saveadder. In yet another embodiment of the invention, the first digitalimage value is represented using a first number of bits and the seconddigital image value is represented using a second number of bits.Moreover, the sum of the left-shifted outputs is represented using athird number of bits and the third number of bits is greater than orequal to the sum of the first number and the second number plus one. Inanother embodiment of the invention, a shift register produces theleft-shifted outputs. And in yet another embodiment, the left-shiftedoutputs are produced by a shifted coupling of outputs of the pluralityof multiplexers to inputs of the adder.

[0008] Another embodiment of the invention is described as a method forperforming alpha blending calculations on a first digital image value Xand a second digital image value Y according to a digital alpha (α)value. The α value has a fractional part of n digits and has a mostsignificant bit of α₁ and a least significant bit of α_(n−1) and theorder of α_(i) is related to i. In the method of the invention, firstand second digital image values are received as well as a value. Themethod then selects either the first or second digital value responsiveto the bit value, α_(i), of α to produce a selected digital value. Theselected digital value is then shifted left according to the order ofthe bit values, α_(i), of α to generate a plurality of left shifteddigital values. The plurality of left-shifted digital values are thenadded to generate a result, R.

[0009] In another embodiment of the invention, the first digital imagevalue is represented using a first number of bits and the second digitalimage value is represented using a second number of bits. Also, the sumof the left-shifted outputs can be represented using a third number ofbits. In an embodiment, the third number of bits is greater than orequal to the sum of the first number and the second number plus one. Inanother embodiment, the first and second left-shifted digital imagevalues are produced by computer controlled bit operations. Also, theadding step can be performed using a hardware-implemented adder.

[0010] Many other embodiments or variations are possible as will beappreciated upon an understanding of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and form apart of this specification, illustrate embodiments of the invention and,together with the description, serve to explain the principles of theinvention:

[0012]FIGS. 1A through 1C illustrate how alpha blending is used to blendat least two different images on one display according to an embodimentof the invention;

[0013]FIG. 2A is a block diagram representation of an implementation forperforming alpha blending calculations using two adders and twomultipliers according to the prior art;

[0014]FIG. 2B is a block diagram representation of an implementation forperforming alpha blending calculations using two adders and onemultiplier according to the prior art;

[0015]FIG. 3 is a flowchart representation of a method for performingalpha blending calculations according to the present invention;

[0016]FIG. 4A is a block diagram representation of an apparatus forperforming alpha blending calculations according to the presentinvention; and

[0017]FIG. 4B is a block diagram representation of an apparatus forperforming alpha blending calculations according to the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] In order to fully understand the present invention, it isimportant to understand the concept of alpha blending. Shown in FIG. 1Ais an image 104 over a background 102. Note that image 104 is in theshape of a four-pointed star with an opaque white (or generally light)color such that the background 102 located behind image 104 is notvisible. Shown in FIG. 1B is an image 106 over a similar background 102.Here, note that image 106 is in the shape of a many-pointed blot with anopaque black (or generally dark) color such that the background 102 isnot visible. There can be many applications where either image 104 orimage 106 are desired to be displayed, however, there are the furtherapplications where a mix or blend of images is desired.

[0019] Shown in FIG. 1C is the condition with a blend of both image 104and image 106. Area 108 is of particularly interest because it is inthis area where image 104 and image 106 intersect and it is this area inwhich individual pixels on a screen must be mixed. Area 108 is thus aresult of blending part of image 104 with part of image 106. In aparticular example, area 108 can be displayed as a contribution of halffrom image 104 and half from image 106. As will be discussed below, thiscan be achieved through alpha blending with a condition where α=0.5.Thus, the resulting area 108 as a blend of opaque white and opaque blackproduces an area 108 that is gray in color.

[0020] In graphics applications, a resulting pixel value, R (e.g., apixel from within area 108), is produced from a blend of a first pixelvalue, X(e.g., a pixel from image 104), and a second pixel value, Y(e.g., a pixel form image 106), through the use of the followingequation:

R=αX+(1−α)Y

[0021] where α is a number ranging from 0 to 1. From this linearequation, it can be seen that where α=1, the resulting pixel value isthe same as the first pixel value (i.e., R=X, when α=1); it is also seenthat where α=0, the resulting pixel value is the same as the secondpixel value (i.e., R=Y, when α=0). It can also be seen that where α=0.5,the resulting pixel value is a blend of both images (i.e., R=0.5X+0.5Y).This is the condition shown for area 108 of FIG. 1C. Many intermediateresults can be achieved by ranging α from 0 to 1.

[0022] Many graphic systems are implemented on digital computers whereinformation including graphical information is communicated in binaryformat. Thus, information is represented as collections of ones andzeros. Moreover, mathematical calculations are performed using a binarycounting system. In order to fully appreciate the present invention, itis important to understand how the prior art performed alpha blendingcalculations.

[0023] Shown in FIG. 2A is a prior art implementation where the alphablending calculation is achieved through the use of two multipliers(i.e., multiplier 204 and multiplier 206) and two adders (i.e., adder202 and adder 208). As shown, digital information for a at input 216 isprovided to adder 202. Also input to adder 202 is a digital value forthe number 1 at input 214. Using techniques known in the art, a result1−α is generated at output 218 of adder 202. Note that, as known in theart, an adder is used to generate a difference, for example by firstnegating the value α. The output 218 and a digital value for Y at input212 is then provided to multiplier 206 to generate the quantity (1−α)Yat output 222. Input to a second multiplier 204 are digital values for Xat input 210 and α at input 216 used to generate the value αX at output220. The values αX and (1−α) Y are then added by adder 208 to generatethe result R=αX+(1−α) Y at output 224.

[0024] Shown in FIG. 2B is another prior art implementation forperforming alpha blending calculations. As shown, adder 202 is used togenerate the quantity X−Y at output 230. Using multiplier 204, thequantity X−Y is multiplied with a to generate the quantity α(X−Y) atoutput 232. Adder 208 is then used to add the quantity α(X−Y) to thevalue Y. The result R=αX+(1−α)Y is then generated at output 224. Ineither the prior art implementation of FIG. 2A or 2B, the multipliers(e.g., 204 or 206) take up a large amount of area on an integratedcircuit. Furthermore, the adders (e.g., 202 or 208) introducesignificant delays in generating an output. Thus, the combinations ofmultipliers and adders take up a large amount of area and introducesignificant delays in generating alpha blending calculations.

[0025] Whereas prior art implementations such as those shown in FIGS. 2Aan 2B, use straightforward mathematical implementations, the presentinvention uses particular characteristics of the digital value α and{overscore (α)} to reduce the amount of integrated circuit area used andthe amount of time needed to generate an alpha blending calculation.Toward understanding the present invention, characteristics of α and{overscore (α)} will be discussed as they relate to alpha blending.

[0026] Given a positive number α in base r with an integer part of mdigits and a fraction part of n digits, the (r−1)'s complement of α isdefined as

{overscore (α)}=r ^(m) −r ^(−n)−α.

[0027] We can apply this to the particular case where r=2 (i.e., abinary or digital system), an integer part of zero digits and a fractionpart of n digits. Thus, the 1's complement of αis defined as

{overscore (α)}=1−r ^(−n)−α.

[0028] Rewriting this result, we have

{overscore (α)}=(1−α)−r ^(−n).

[0029] For n of sufficient size, it is observed that the term r^(−n)becomes very small such that the 1 's complement of a is approximated as

{overscore (α)}≈(1−α).

[0030] Whereas the calculation of the 1's complement of α can bemathematically complex, in actual implementation, the 1's complement isachieved by simply reversing each bit of a digital number. For example,for the digital number α=0.01101001 (i.e., α=0.41015625 in base 10), the1's complement is achieved by simply reversing each bit resulting in the1's complement {overscore (α)}=0.10010110 (i.e., {overscore(α)}=0.5859375 in base 10; note that for the purposes of the presentdisclosure, leading zeros will be omitted when referring to digitalnumbers if no bit is present to represent the leading zero). We see that{overscore (α)}=0.5859375 closely approximates the true value of1−α=0.58984375 where the difference is equal to 2⁻⁸=0.00390625. Thus,because the complement of a can be easily obtained, so can anapproximation of the quantity 1−α. A fast and efficient manner forcalculating the quantity (1-a) is developed from this approximation.Moreover, a fast and efficient manner for performing alpha blending isdeveloped.

[0031] Recall that the alpha blending calculation takes two quantities Xand Y and blends them together according to a value α to produce a mixedvalue R according to the equation:

R=αX+(1−α)Y.

[0032] From the approximation for {overscore (α)}, we obtain an estimatefor the value R:

R≈αX+{overscore (α)}Y

[0033] where {overscore (α)}≈(1−α).

[0034] We can therefore rewrite the equation for R as${R \approx {{\left( {\sum\limits_{i = 0}^{n - 1}\quad {\alpha_{i}2^{{- i} - 1}}} \right)X} + {\left( {\sum\limits_{i = 0}^{n - 1}\quad {{\overset{\_}{\alpha}}_{i}2^{{- i} - 1}}} \right)Y}}} = {\sum\limits_{i = 0}^{n - 1}\quad R_{i}}$

[0035] where

[0036] α₁ (sometimes also written as α(1)) is the most significant bit(MSB) of α,

[0037] α_(n−1) (sometimes also written as α(n−1) is the leastsignificant bit (LSB) of α,

[0038] {overscore (α)}₁ (sometimes also written as α(1)) is the MSB of{overscore (α)},

[0039] {overscore (α)}_(n−1) (sometimes also written as {overscore(α)}(n−1) is the LSB of {overscore (α)}; and

[0040] R_(i) is a partial sum corresponding to α_(i) or {overscore(α)}_(i).

[0041] From the approximation for R above, the number i corresponds in aknown way to the order of the bit value α_(i). Consider, for example,the partial sum

R _(i)=α_(i)2^(−i−1) X+{overscore (α)},2^(−i−1) Y

[0042] where i=2, α₂=1 and {overscore (α)}₂=0 such that we have thefollowing partial sum$R_{2} = {{{\alpha_{2} \cdot 2^{- 3} \cdot X} + {{\overset{\_}{\alpha}}_{2} \cdot 2^{- 3} \cdot Y}}\quad = {{{1 \cdot 2^{- 3} \cdot X} + {0 \cdot 2^{- 3} \cdot Y}}\quad = {2^{- 3} \cdot {X.}}}}$

[0043] Now consider, for example, the condition where i=3, a 3=0, and a3=1 such that we have the following partial sum$R_{3} = {{{\alpha_{3} \cdot 2^{- 4} \cdot X} + {{\overset{\_}{\alpha}}_{3} \cdot 2^{- 4} \cdot Y}}\quad = {{{0 \cdot 2^{- 4} \cdot X} + {1 \cdot 2^{- 4} \cdot Y}}\quad = {2^{- 4} \cdot {Y.}}}}$

[0044] It is, therefore, observed that the result R is obtained as thesum of left-shifted digital quantities of the quantities X and Y, wherethe quantities X and Y are left-shifted according to the order of thecorresponding bit of α or {overscore (α)}, respectively. Because thequantities α and {overscore (α)} are complements of each other, it isfurther observed that any partial sum, R_(i), is obtained from either ashifted quantity of X or Y, but not both.

[0045] An example will assist in understanding the concepts justdescribed. Assume that X and Y are 8-bit numbers. For the purposes ofclarity the subscript 8 (i.e., X₈ and Y₈) will be used to remind thereader that these are 8-bit values; moreover, the subscript 8 will beused with the value zero (i.e., 0₈) to denote an 8-bit zero value.Assume that α is an eight-bit number less than 1 and greater than orequal to zero such that {overscore (α)} is also less than 1 and greaterthan or equal to zero. In proceeding, specific values of α and{overscore (α)} will be used to illustrate key features of the presentinvention, but one of skill in the art will understand its broadimplications. If α=0.011001, then {overscore (α)}=0.10010110. Theproduct α·X₈ is, therefore, conceptually obtained as follows:$\left. {\alpha \cdot X_{8}}\Rightarrow\begin{matrix}\quad & 0 & \quad & 1 & \quad & 1 & \quad & 0 & \quad & 1 & \quad & 0 & \quad & 0 & \quad & 1 \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\x & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & X_{8} \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & X_{8} \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & 0_{8} & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & 0_{8} & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & X_{8} & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & 0_{8} & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & X_{8} & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & X_{8} & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & 0_{8} & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & 0_{{8{L7}},} & + & X_{8,{L6}} & + & X_{8,{L5}} & + & 0_{8,{L4}} & + & X_{8,{L3}} & + & 0_{8,{L2}} & + & 0_{8,{L1}} & + & X_{8,{L0}} \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad\end{matrix} \right.$

[0046] Note that in this result,0_(8,L7)+X_(8,L6)+X_(8,L 5)+0_(8,L4)+X_(8,L3)+0_(8,L2)+0_(8,L1+X)_(8,L0), the subscript Lx has been included to denote the number of leftshifts associated with a value (e.g., L7 indicates a left shift of 7bits). Thus, to obtain the product α·X₈ requires shifting of the valueX₈ according to the digital representation of α. Where a 1 is present inthe digital value α_(i), the digital value X₈ is shifted left accordingto the order of α_(i) such that the final product α·X₈ is the sum of allthe shifted values; zero values do not add to the complexity of thepresent calculation, but are included here as place holders towardobtaining a final solution. Placement of the decimal point must accountfor the fractional number α and the fractional part of the value X₈ asis known to those of skill in the art. Similarly, with the 1'scomplement of α, the product {overscore (α)}·Y₈ is obtained as follows$\left. {\overset{\_}{\alpha} \cdot Y_{8}}\Rightarrow\begin{matrix}\quad & 1 & \quad & 0 & \quad & 0 & \quad & 1 & \quad & 0 & \quad & 1 & \quad & 1 & \quad & 0 \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\x & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & Y_{8} \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & 0_{8} \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & Y_{8} & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & Y_{8} & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & 0_{8} & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & Y_{8} & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & 0_{8} & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & 0_{8} & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & Y_{8} & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad \\\quad & Y_{{8{L7}},} & + & 0_{8,{L6}} & + & 0_{8,{L5}} & + & Y_{8,{L4}} & + & 0_{8,{L3}} & + & Y_{8,{L2}} & + & Y_{8,{L1}} & + & 0_{8,{L0}} \\\quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad & \quad\end{matrix} \right.$

[0047] The quantity R can, therefore, be obtained by adding thesecalculated values: $\left. R\Rightarrow\begin{matrix}\begin{matrix}0_{{8{L7}},} & + & X_{8,{L6}} & + & X_{8,{L5}} & + & 0_{8,{L4}} & + & X_{8,{L3}} & + & 0_{8,{L2}} & + & 0_{8,{L1}} & + & X_{8,{L0}}\end{matrix} \\\begin{matrix}{\quad Y_{{8{L7}},}} & + & 0_{8,{L6}} & + & 0_{8,{L5}} & + & Y_{8,{L4}} & + & 0_{8,{L3}} & + & Y_{8,{L2}} & + & Y_{8,{L1}} & + & 0_{{8,{L0}}\quad} \\{\quad Y_{{8{L7}},}} & + & X_{8,{L6}} & + & X_{8,{L5}} & + & Y_{8,{L4}} & + & X_{8,{L3}} & + & Y_{8,{L2}} & + & Y_{8,{L1}} & + & X_{{8,{L0}}\quad}\end{matrix}\end{matrix} \right.$

[0048] Observe that the values of X_(8,Ly) and Y_(8,Ly) (where y is avalue between 0 and 7) are never added to each other such that only oneor the other of the shifted values, X_(8,Ly) and Y_(8,Ly), can be inputto an adder to calculate the resulting sum. The adder used in such afunction would need to account for possible carries of the resultingsum,Y_(8,L7)+X_(8,L6)+X_(8,L5)+Y_(8,L4)+X_(8,L3)+Y_(8,L2)+Y_(8,L1)+X_(8,L0).

[0049] It is further observed that an approximate value for R can beobtained by selecting either X or Y according to the digitalrepresentation of ≢, shifting the selected value according to the orderof α_(i) and then adding the selected and shifted quantities (note thathere no subscripts are used on X and Y because the more general case isbeing discussed).

[0050] Shown in FIG. 3 is a flowchart corresponding to a method 300 ofthe present invention implementing the observations described above. Toassure that values are properly controlled in method 300, a resultvalue, R, of n digits is initialized at step 302 and a counter, i, isinitialized at step 304. A query is then made at step 306 as to whetheror not the present value of the counter, i, is less than or equal to thevalue n−1. In a first pass of the method 300 with n greater than orequal to 1, step 306 would yield a TRUE condition. A query would then bemade as to whether or not the i^(th) bit of α is equal to 1 (i.e.,α_(i)=1?) at step 308. Where step 308 yields a TRUE condition, step 310is executed. At step 310, an intermediate value R_(i) is generated equalto the value 2^(−i−1)·X. Where step 308 yields a FALSE condition (i.e.,α_(i)=0, that is, {overscore (α)}_(i)=1), step 312 is executed. At step312, an intermediate value R_(i) is generated equal to the value2^(−i−1)·Y. After the execution of either step 310 or 312, the step 314is executed where a new value for the result, R, is obtained by addingthe intermediate value, R_(i), obtained in either step 310 or 312. Step314 is not a general addition, but is rather an addition as would becomputed by computer in implementing a programming language such as C orC++. The counter, i, is then incremented at step 316 after which thequery of step 306 is again made. When the query of step 306 yields aFALSE condition, a final result is obtained as the value R at step 318.One of skill in the art will understand that improvements can be made ofmethod 300 without deviating from the general method described. Forexample, step 314 can be absorbed into steps 310 and 312 such that anintermediate result, R_(i), need not be generated. Furthermore, thecounter, i, can be implemented in more efficient manners as known to oneof skill in the art.

[0051] The method 300 of FIG. 3 lends itself to implementation in adigital computer; however, method 300 can also be implemented inhardware for fast and cost-effective computation of alpha blendingcalculations. A block diagram of a hardware implementation is shown inFIG. 4A. Shown in FIG. 4A is an implementation wherein the values X at404, Y at 402, and α are eight-bit binary numbers. With the presentdisclosure, however, one of skill in the art will understand the moregeneral applicability of FIG. 4A. As shown in FIG. 4A, the values X andY are directed to the inputs of multiplexers 408-0 through 408-7. Here,note that the eight-bit values for X and Y are directed to the inputs ofeach of the multiplexers 408-0 through 408-7. As further shown in FIG.4A, the various bits of the value α are directed to the select lines ofmultiplexers 408-0 through 408-7. The least significant bit of α, α₀, isdirected to multiplexer 408-0 and the most significant bit of α, α₇, isdirected to multiplexer 408-7. Intermediate bits of α are similarlydirected to corresponding multiplexers. Thus, the bits of α are used toselect from the eight-bit values X or Y. Where a bit of α_(i)=1, thevalue X is selected; where a bit of α_(i)=0 corresponding to a bit of{overscore (α)}_(i)=1, the value Y is selected.

[0052] Recall that various left shifts of X and Y were required toobtain the value R=αX+{overscore (α)}Y. Left shift units 412-0 through412-7 provide this shifting function. In actual implementation, leftshift unit 412-0 can be omitted, as no shift is required. It isnonetheless included so as to highlight the symmetry of implementation.In an embodiment of the invention, left shift units 412-0 through 412-7are shift registers. It is further noted that the function of left shiftunits 412-0 through 412-7 can be readily implemented in various wayswithout introducing a separate device. For example, shifting a valueleft can be achieved through wiring a device with shifted inputs oroutputs. Moreover, where a digital computer is in use, the digitalcomputer can readily provide shifted values of either X or Y.

[0053] The outputs of left shift units 412-0 through 412-7 are thendirected to adder 414. One of skill in the art will understand thatadder 414 can be implemented in many forms. In an embodiment of theinvention, adder 414 is implemented as a carry-save adder (CSA). Theoutput at 418 of adder 414 is therefore the desired result, R. In theembodiment being described, adder 414 provides 17 bit lines to representthe result R.

[0054] To further highlight features of the present invention, FIG. 4Awill now be described as a continuation of the previously-describedexample where α=0.01101001 and {overscore (α)}=0.10010110. The bitvalues of α are directed to the select lines of multiplexers 408-0through 408-7 with the most significant bit (MSB) of α directed to theselect line of multiplexer 408-7 and the least significant bit (LSB) ofa directed to the select line of multiplexer 408-0. With α=0.01101001,the outputs of multiplexers 408-7 through 408-0 are respectively Y, X,X, Y, X, Y, Y, and X. Accordingly, the output of multiplexer 408-7(i.e., Y) is shifted left 7 bits to generate Y_(L7), the output ofmultiplexer 408-6 (i.e., X) is shifted left 6 bits to generate X_(L6),the output of multiplexer 408-5 (i.e., X) is shifted left 5 bits togenerate X_(L5), the output of multiplexer 408-4 (i.e., Y) is shiftedleft 4 bits to generate Y_(L4), the output of multiplexer 408-3 (i.e.,X) is shifted left 3 bits to generate X_(L3), the output of multiplexer408-2 (i.e., y) is shifted left 2 bits to generate Y_(L2), the output ofmultiplexer 408-1 (i.e., Y) is shifted left 1 bit to generate Y_(L1),and the output of multiplexer 408-0 (i.e., X) is shifted left 0 bits,i.e., no shifting is necessary, to generate X_(L0). These shifted valuesare then directed to the inputs 416-7 through 416-0, respectively, ofadder 414 that produces the result R at output 418. Note that foreight-bit values for X and Y require 17 bits at the output R.

[0055] Another embodiment of the present invention is shown in FIG. 4B.Many of the features of FIG. 4B are similar to that of FIG. 4A, exceptthat values of X and Y are shifted prior to being input to multiplexers408-0 through 408-1. In FIG. 4B, two left shift units are associatedwith each multiplexer 408-0 through 408-7. Upon selection of by theappropriate bit value of α the correctly shifted values of either X or Yare directed to inputs 416-0 through 416-7 of adder 414. As describedwith reference to FIG. 4A, adder 414 can be implemented by various typesof adders including, for example, a carry save adder (CSA). The result Rat output 418 is thus the correct result for the alpha blendingcalculation.

[0056] It is noted that implementations of the present invention shownin FIGS. 4A and 4B use much less area and are much faster than the priorart implementations shown in FIGS. 2A and 2B. Importantly, multiplexers408-0 through 408-7 take up very little chip area and introduce verylittle latency. Adder 414 is more complex than adders 202 and 208 ofFIG. 2. In fact, adder 414 is of the order of a prior art multipliersuch as multipliers 204 and 206; however, the latency of adder 414 isstill approximately the same as prior art adders such as adders 202 and208. Thus as a whole, the present invention provides alpha blendingcalculations using chip area on the order of one prior art multiplierand a latency of one prior art adder.

[0057] The foregoing descriptions of specific embodiments of the presentinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise forms disclosed. Many modifications andvariations are possible in light of the above teachings withoutdeviation from the scope of the claims set out below. The embodimentswere chosen and described in order to best explain the principles of theinvention and its practical application, to thereby enable othersskilled in the art to best utilize the invention and various embodimentswith various modifications as are suited to the particular usecontemplated.

What is claimed is:
 1. An apparatus for performing alpha blendingcalculations on a first digital image value and a second digital imagevalue according to a digital alpha (α) value having a fractional part ofn digits and having a most significant bit of α_(i) and a leastsignificant bit of α_(n−1), and wherein the order of α_(i) is related toan i^(th) digit of α, comprising: a plurality of multiplexers, each ofthe plurality of multiplexers configured to receive a bit value, α_(i),of the digital value α, each of the plurality of multiplexers configuredto receive the first and second digital image values, each of theplurality of multiplexers configured to direct to outputs of theplurality of multiplexers either the first or second digital image valueresponsive to the bit value, α_(i), of the digital value α, each of theoutputs of the plurality of multiplexers shifted left according to theorder of the bit values, α_(i), of α in order to produce a plurality ofleft-shifted outputs; and an adder configured to receive the pluralityof left-shifted outputs and further configured to produce the sum of theleft-shifted outputs.
 2. The apparatus of claim 1, wherein the adder isa carry save adder.
 3. The apparatus of claim 1, wherein the firstdigital image value is represented using a first number of bits and thesecond digital image value is represented using a second number of bits.4. The apparatus of claim 3, wherein the sum of the left-shifted outputsis represented using a third number of bits.
 5. The apparatus of claim4, wherein the third number of bits is greater than or equal to the sumof the first number and the second number plus one.
 6. The apparatus ofclaim 1, wherein the left-shifted outputs are produced by a shiftregister.
 7. The apparatus of claim 1, wherein the left-shifted outputsare produced by a shifted coupling of outputs of the plurality ofmultiplexers to inputs of the adder.
 8. An apparatus for performingalpha blending calculations on a first digital image value and a seconddigital image value according to a digital alpha (α) value having afractional part of n digits and having a most significant bit of α_(i)and a least significant bit of α_(n−1), and wherein the order of α_(i)is related to an i^(th) digit of α, comprising: a plurality ofmultiplexers, each of the plurality of multiplexers configured toreceive a bit value, α_(i), of the digital value α, each of theplurality of multiplexers configured to receive first and secondleft-shifted digital image values, the first and second left-shifteddigital image values shifted left according to the order of the bitvalues, α_(i), of α, each of the plurality of multiplexers configured toproduce a plurality of left-shifted outputs by directing to outputs ofthe plurality of multiplexers either the first or second left-shifteddigital image value responsive to the bit value, α_(i), of α; and anadder configured to receive the plurality of left-shifted outputs andfurther configured to produce the sum of the left-shifted outputs. 9.The apparatus of claim 8, wherein the adder is a carry save adder. 10.The apparatus of claim 8, wherein the first digital image value isrepresented using a first number of bits and the second digital imagevalue is represented using a second number of bits.
 11. The apparatus ofclaim 10, wherein the sum of the left-shifted outputs is representedusing a third number of bits.
 12. The apparatus of claim 11, wherein thethird number of bits is greater than or equal to the sum of the firstnumber and the second number plus one.
 13. The apparatus of claim 8,wherein the first and second left-shifted digital image values areproduced by a shift register.
 14. The apparatus of claim 8, wherein theleft-shifted outputs are produced by a shifted coupling of inputs of theplurality of multiplexers.
 15. A method for performing alpha blendingcalculations on a first digital image value X and a second digital imagevalue Y according to a digital alpha (α) value having a fractional partof n digits and having a most significant bit of α₁ and a leastsignificant bit of α_(n−1), and wherein the order of α_(i) is i,comprising: receiving the first and second digital image values;receiving the α value; selecting the first digital value responsive to alogical high of the bit value, α_(i), of α, otherwise selecting thesecond digital value responsive to a logical low of the bit value,α_(i), of α, the selected first or second digital value being a selecteddigital value, and shifting the selected digital value left according tothe order of the bit values, α_(i), of α to generate a plurality of leftshifted digital values; and adding the plurality of left-shifted digitalvalues to generate a result, R.
 16. The method of claim 15, wherein thefirst digital image value is represented using a first number of bitsand the second digital image value is represented using a second numberof bits.
 17. The method of claim 16, wherein the sum of the left-shiftedoutputs is represented using a third number of bits.
 18. The method ofclaim 17, wherein the third number of bits is greater than or equal tothe sum of the first number and the second number plus one.
 19. Themethod of claim 15, wherein the first and second left-shifted digitalimage values are produced by computer controlled bit operations.
 20. Themethod of claim 15, wherein the adding step is performed using ahardware implemented adder.
 21. An apparatus for performing alphablending calculations on a first digital image value and a seconddigital image value according to a digital alpha (α) value having afractional part of n digits and having a most significant bit of α₁ anda least significant bit of α_(n−1), and wherein the order of α_(i) isrelated to an i^(th) digit of α, comprising: means for receiving thefirst and second digital image values; means for receiving the α value;means for selecting the first digital value responsive to a logical highof the bit value, α_(i), of α, otherwise selecting the second digitalvalue responsive to a logical low of the bit value, α_(i), of α, theselected first or second digital value being a selected digital value,and means for shifting the selected digital value left according to theorder of the bit values, α_(i), of α to generate a plurality of leftshifted digital values; and means for adding the plurality ofleft-shifted digital values to generate a result, R.
 22. The apparatusof claim 21, wherein the first digital image value is represented usinga first number of bits and the second digital image value is representedusing a second number of bits.
 23. The apparatus of claim 22, whereinthe sum of the left-shifted outputs is represented using a third numberof bits.
 24. The apparatus of claim 23, wherein the third number of bitsis greater than or equal to the sum of the first number and the secondnumber plus one.
 25. The apparatus of claim 21, wherein the first andsecond left-shifted digital image values are produced by computercontrolled bit operations.
 26. The apparatus of claim 21, wherein themeans for adding is a hardware implemented adder.
 27. A computer programproduct embodying a program of instructions executable by a machine toperform method steps for performing alpha blending calculations on afirst digital image value X and a second digital image value Y accordingto a digital alpha (α) value having a fractional part of n digits andhaving a most significant bit of α₁ and a least significant bit ofα_(n−1), and wherein the order of α_(i) is i, said product beingoperative to execute a method comprising: receiving the first and seconddigital image values; receiving the α value; selecting the first digitalvalue responsive to a logical high of the bit value, α_(i), of α,otherwise selecting the second digital value responsive to a logical lowof the bit value, α_(i), of α, the selected first or second digitalvalue being a selected digital value, and shifting the selected digitalvalue left according to the order of the bit values, α_(i), of α togenerate a plurality of left shifted digital values; and adding theplurality of left-shifted digital values to generate a result, R.
 28. Acomputer program product as recited in claim 27, wherein the firstdigital image value is represented using a first number of bits and thesecond digital image value is represented using a second number of bits.29. A computer program product as recited in claim 28, wherein the sumof the left-shifted outputs is represented using a third number of bits.30. A computer program product as recited in claim 29, wherein the thirdnumber of bits is greater than or equal to the sum of the first numberand the second number plus one.
 31. A computer program product asrecited in claim 27, wherein the first and second left-shifted digitalimage values are produced by computer controlled bit operations.
 32. Acomputer program product as recited in claim 27, wherein the adding stepis performed using a hardware implemented adder.